no way to compare when less than two revisions
Differences
This shows you the differences between two versions of the page.
— | cybiko:h8portmap [2009/11/27 17:54] (current) – created - external edit 127.0.0.1 | ||
---|---|---|---|
Line 1: | Line 1: | ||
+ | ======Cybiko Port Map - using H8S 2241====== | ||
+ | Lifted and amended from http:// | ||
+ | |||
+ | To access these ports using bytecode see [[RegisterAccess]] | ||
+ | |||
+ | |||
+ | =====Port 1===== | ||
+ | |||
+ | Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, | ||
+ | TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and | ||
+ | an address bus output function. Port 1 pin functions change according to the operating mode. | ||
+ | |||
+ | ^ Name ^ R/W ^ Address ^ | ||
+ | | Data direction register | W | 0xFEB0 | | ||
+ | | Data register | R/W | 0xFF60 | | ||
+ | | Read | R | 0xFF50 | | ||
+ | |||
+ | 7 - TIOCB2 - Exp Port 54 - CS for serial EEPROM | ||
+ | 6 - TIOCA2 - vibrator | ||
+ | 5 - TIOCB1 - speaker | ||
+ | 4 - TIOCA1 - Exp Port 53 - CS for serial EEPROM | ||
+ | 3 - TIOCD0 - NC | ||
+ | 2 - TIOCC0 - +3.3v | ||
+ | 1 - TIOCB0 - Exp Port 50 | ||
+ | 0 - TIOCA0 - Exp Port 59 | ||
+ | |||
+ | =====Port 2===== | ||
+ | |||
+ | Port 2 is an 8-bit I/O port. Port 2 pins also function as 8-bit timer I/O pins (TMRI0, TMCI0, | ||
+ | TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. | ||
+ | Port 2 uses Schmitt-triggered input. | ||
+ | |||
+ | ^ Name ^ R/W ^ Address | | ||
+ | | Data direction register | W | 0xFEB1 | | ||
+ | | Data register | R/W | 0xFF61 | | ||
+ | | Read | R | 0xFF51 | | ||
+ | |||
+ | 7 - TMO1 - Exp Port 55 - serial clock | ||
+ | 6 - TMO0 - Reset Atmel uC - Active Low | ||
+ | 5 - TMCI1 - NC | ||
+ | 4 - TMRI1 - Powerdown RF LMX2315 - Active Low | ||
+ | 3 - TMCI0 - Green Led - Active High | ||
+ | 2 - TMRI0 - Red Led - Active High | ||
+ | 1 - P21 - Exp Port 44 - chip select? | ||
+ | 0 - P20 - NC | ||
+ | |||
+ | =====Port 3===== | ||
+ | |||
+ | Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, | ||
+ | RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are the same in all | ||
+ | operating modes. The interrupt input pins (IRQ4, IRQ5) are Schmitt-triggered inputs. | ||
+ | |||
+ | |||
+ | ^ Name ^ R/W ^ Address | | ||
+ | | Data direction register | W | 0xFEB2 | | ||
+ | | Data register | R/W | 0xFF62 | | ||
+ | | Read | R | 0xFF52 | | ||
+ | | Open drain control Reg | R | 0xFF76 | | ||
+ | |||
+ | |||
+ | 5 - SCK1 - clock Exp Port | ||
+ | 4 - SCK0 - CEF - Exp Port | ||
+ | 3 - RXD1 - Exp Port: Dout | ||
+ | 2 - RXD0 - Receive from Atmel (RF) | ||
+ | 1 - TXD1 - Exp Port: Din | ||
+ | 0 - TXD0 - Transmit toward Atmel (RF) | ||
+ | |||
+ | =====Port 4===== | ||
+ | |||
+ | Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins | ||
+ | (AN0 to AN3). Port 4 pin functions are the same in all operating modes. Figure 8-4 shows the port | ||
+ | 4 pin configuration. | ||
+ | |||
+ | |||
+ | ^ Name ^ R/W ^ Address | | ||
+ | | Read | R | 0xFF53 | | ||
+ | |||
+ | 3 - AN3 - NC | ||
+ | 2 - AN2 - battery level | ||
+ | 1 - AN1 - battery level | ||
+ | 0 - AN0 - RF Signal Strength | ||
+ | |||
+ | =====Port 5===== | ||
+ | |||
+ | Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2). Port | ||
+ | 5 pin functions are the same in all operating modes. Figure 8-5 shows the port 5 pin configuration. | ||
+ | |||
+ | |||
+ | ^ Name ^ R/W ^ Address | | ||
+ | | Data direction register | W | 0xFEB4 | | ||
+ | | Data register | R/W | 0xFF64 | | ||
+ | | Read | R | 0xFF54 | | ||
+ | |||
+ | |||
+ | 3 - P53 - Charge circuitry enable - Active High | ||
+ | 2 - SCK2 - NC | ||
+ | 1 - RXD2 - RS232 receive | ||
+ | 0 - TXD2 - RS232 transmit | ||
+ | |||
+ | Port A - address lines A19 - A16\\ | ||
+ | Port B - Address lines A15 - A8\\ | ||
+ | Port C - Address lines A7 - A0\\ | ||
+ | Port D - Data lines D15 - D8\\ | ||
+ | Port E - Data lines D7 - D0 | ||
+ | |||
+ | =====Port F===== | ||
+ | |||
+ | Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/ | ||
+ | RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK), the system clock (ø) output pin and | ||
+ | interrupt input pins (IRQ0 to IRQ3). | ||
+ | The interrupt input pins (IRQ0 to IRQ3) are Schmitt-triggered inputs. | ||
+ | |||
+ | |||
+ | ^ Name ^ R/W ^ Address | | ||
+ | | Data direction register | W | 0xFEBE | | ||
+ | | Data register | R/W | 0xFF6E | | ||
+ | | Read | R | 0xFF5E | | ||
+ | |||
+ | |||
+ | 7 - F0 - NC | ||
+ | 6 - AS# - NC | ||
+ | 5 - RD# - read enable - Active Low | ||
+ | 4 - HWR# - write enable - Active Low | ||
+ | 3 - IRQ3/LWR# - NC | ||
+ | 2 - IRQ2 - R_BF - ready line | ||
+ | 1 - IRQ1# - SCL - Real Time Clock - clock | ||
+ | 0 - IRQ0# - SDA - Real Time Clock - data | ||
+ | |||
+ | =====Port G===== | ||
+ | |||
+ | Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3). | ||
+ | The A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The interrupt input | ||
+ | pins (IRQ6, IRQ7) are Schmitt-triggered inputs. | ||
+ | |||
+ | |||
+ | ^ Name ^ R/W ^ Address | | ||
+ | | Data direction register | W | 0xFEBF | | ||
+ | | Data register | R/W | 0xFF6F | | ||
+ | | Read | R | 0xFF5F | | ||
+ | |||
+ | |||
+ | 4 - CS0# - NC | ||
+ | 3 - CS1# - Ram Chip Enable | ||
+ | 2 - CS2# - Expansion Enable | ||
+ | 1 - CS3# - LCD Enable | ||
+ | 0 - IRQ6# - NC |